#!/usr/bin/python """ stage 2 of 3 challenge: reveal the solution within VM.mem Nick Craig-Wood http://www.craig-wood.com/nick/ """ from array import array CS = 4 DS = 5 JMP = 0x00 MOVR = 0x01 MOVM = 0x02 ADD = 0x03 XOR = 0x04 CMP = 0x05 JMPE = 0x06 HLT = 0x07 MEMSIZE = 16*256 MEMMASK = MEMSIZE -1 class VM(object): """ virtual machine architecture ++++++++++++++++++++++++++++ segmented memory model with 16-byte segment size (notation seg:offset) 4 general-purpose registers (r0-r3) 2 segment registers (cs, ds equiv. to r4, r5) 1 flags register (fl) flags +++++ cmp r1, r2 instruction results in: r1 == r2 => fl = 0 r1 < r2 => fl = 0xff r1 > r2 => fl = 1 jmpe r1 => if (fl == 0) jmp r1 else nop """ def __init__(self, debug=False): self.debug = debug self.ip = 0x00 self.instruction_ip = self.ip self.r = [0x00, 0x00, 0x00, 0x00, 0x00, 0x10] # r0..r3,cs,ds self.cycle_count = 0 #self.r0 = 0x00 #self.r1 = 0x00 #self.r2 = 0x00 #self.r3 = 0x00 #self.cs = 0x00 #self.ds = 0x10 self.fl = 0x00 #self.firmware = [0xd2ab1f05, 0xda13f110] self.firmware = [0xd2,0xab,0x1f,0x05,0xda,0x13,0xf1,0x10] #self.firmware = [0x05,0x1f,0xab,0xd2,0x10,0xf1,0x13,0xda] self.dispatch = { (JMP, 0) : self.do_jmp_r1, (JMP, 1) : self.do_jmp_r2_r1, (MOVR, 0) : self.do_movr_r2_r1, (MOVR, 1) : self.do_movr_rx_imm, (MOVM, 0) : self.do_movm_r1_ds_r2, (MOVM, 1) : self.do_movm_ds_r1_r2, (ADD, 0) : self.do_add_r2_r1, (ADD, 1) : self.do_add_r1_imm, (XOR, 0) : self.do_xor_r2_r1, (XOR, 1) : self.do_xor_r1_imm, (CMP, 0) : self.do_cmp_r2_r1, (CMP, 1) : self.do_cmp_r1_imm, (JMPE, 0) : self.do_jmpe_r1, (JMPE, 1) : self.do_jmpe_r2_r1, (HLT, 0) : self.do_hlt, (HLT, 1) : self.do_hlt, } initial = [ 0x31, 0x04, 0x33, 0xaa, 0x40, 0x02, 0x80, 0x03, 0x52, 0x00, 0x72, 0x01, 0x73, 0x01, 0xb2, 0x50, 0x30, 0x14, 0xc0, 0x01, 0x80, 0x00, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0xd7, 0xcd, 0x87, 0xa3, 0xd3, 0x6b, 0x36, 0x6f, 0x6f, 0x66, 0x55, 0x30, 0x16, 0x45, 0x5e, 0x09, 0x74, 0x5c, 0x3f, 0x29, 0x2b, 0x66, 0x3d, 0x0d, 0x02, 0x30, 0x28, 0x35, 0x15, 0x09, 0x15, 0xdd, 0xec, 0xb8, 0xe2, 0xfb, 0xd8, 0xcb, 0xd8, 0xd1, 0x8b, 0xd5, 0x82, 0xd9, 0x9a, 0xf1, 0x92, 0xab, 0xe8, 0xa6, 0xd6, 0xd0, 0x8c, 0xaa, 0xd2, 0x94, 0xcf, 0x45, 0x46, 0x67, 0x20, 0x7d, 0x44, 0x14, 0x6b, 0x45, 0x6d, 0x54, 0x03, 0x17, 0x60, 0x62, 0x55, 0x5a, 0x4a, 0x66, 0x61, 0x11, 0x57, 0x68, 0x75, 0x05, 0x62, 0x36, 0x7d, 0x02, 0x10, 0x4b, 0x08, 0x22, 0x42, 0x32, 0xba, 0xe2, 0xb9, 0xe2, 0xd6, 0xb9, 0xff, 0xc3, 0xe9, 0x8a, 0x8f, 0xc1, 0x8f, 0xe1, 0xb8, 0xa4, 0x96, 0xf1, 0x8f, 0x81, 0xb1, 0x8d, 0x89, 0xcc, 0xd4, 0x78, 0x76, 0x61, 0x72, 0x3e, 0x37, 0x23, 0x56, 0x73, 0x71, 0x79, 0x63, 0x7c, 0x08, 0x11, 0x20, 0x69, 0x7a, 0x14, 0x68, 0x05, 0x21, 0x1e, 0x32, 0x27, 0x59, 0xb7, 0xcf, 0xab, 0xdd, 0xd5, 0xcc, 0x97, 0x93, 0xf2, 0xe7, 0xc0, 0xeb, 0xff, 0xe9, 0xa3, 0xbf, 0xa1, 0xab, 0x8b, 0xbb, 0x9e, 0x9e, 0x8c, 0xa0, 0xc1, 0x9b, 0x5a, 0x2f, 0x2f, 0x4e, 0x4e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ] initial.extend([0] * (MEMSIZE-len(initial))) self.mem = array('B', initial) assert len(self.mem) == MEMSIZE def read_op(self): """ Reads a code byte from ip and advances it """ op = self.mem[(self.r[CS] * 16 + self.ip) & MEMMASK] self.ip = (self.ip + 1) & 0xFF # FIXME does the code segment wrap or not? return op def trace(self, instruction): if self.debug: print "%02x:%02x: %-20s r0=%02x,r1=%02x,r2=%02x,r3=%02x,cs=%02x,ds=%02x,fl=%02x" % (self.r[CS], self.instruction_ip, instruction, self.r[0], self.r[1], self.r[2], self.r[3], self.r[CS], self.r[DS], self.fl) def do_jmp_r1(self, r1, _): """jmp r1 """ self.trace("jmp r%d" % r1) self.ip = self.r[r1] def do_jmp_r2_r1(self, r1, r2): """jmp r2:r1 """ self.trace("jmp #0x%02x:r%d" % (r2,r1)) self.r[CS] = r2 # This wasn't at all clear in the docs self.ip = self.r[r1] def do_movr_r2_r1(self, r1, r2): """movr r1, r2 """ self.trace("movr r%d, r%d" % (r1, r2)) self.r[r1] = self.r[r2] def do_movr_rx_imm(self, r1, imm): """movr rx, imm """ self.trace("movr r%d, #0x%02x" % (r1, imm)) self.r[r1] = imm def do_movm_r1_ds_r2(self, r1, r2): """movm r1, [ds:r2] """ self.trace("movr r%d, [ds:r%d]" % (r1, r2)) self.r[r1] = self.mem[(self.r[DS]*16+self.r[r2]) & MEMMASK] def do_movm_ds_r1_r2(self, r1, r2): """movm [ds:r1], r2 """ self.trace("movr [ds:r%d], r%d" % (r1, r2)) self.mem[(self.r[DS]*16 + self.r[r1]) & MEMMASK] = self.r[r2] def do_add_r2_r1(self, r1, r2): """add r1, r2 """ self.trace("add r%d, r%d" % (r1, r2)) self.r[r1] = (self.r[r1] + self.r[r2]) & 0xFF def do_add_r1_imm(self, r1, imm): """add r1, imm """ self.trace("add r%d, #0x%02x" % (r1, imm)) self.r[r1] = (self.r[r1] + imm) & 0xFF def do_xor_r2_r1(self, r1, r2): """xor r1, r2 """ self.trace("xor r%d, r%d" % (r1, r2)) self.r[r1] = self.r[r1] ^ self.r[r2] def do_xor_r1_imm(self, r1, imm): """xor r1, imm """ self.trace("add r%d, #0x%02x" % (r1, imm)) self.r[r1] = self.r[r1] ^ imm def _do_cmp(self, v1, v2): """ cmp r1, r2 instruction results in: r1 == r2 => fl = 0 r1 < r2 => fl = 0xff r1 > r2 => fl = 1 """ if v1 == v2: self.fl = 0x00 elif v1 < v2: self.fl = 0xff else: self.fl = 1 def do_cmp_r2_r1(self, r1, r2): """cmp r1, r2 """ self.trace("cmp r%d, r%d" % (r1, r2)) self._do_cmp(self.r[r1], self.r[r2]) def do_cmp_r1_imm(self, r1, imm): """cmp r1, imm """ self.trace("cmp r%d, #0x%02x" % (r1, imm)) self._do_cmp(self.r[r1], imm) def do_jmpe_r1(self, r1, _): """jmpe r1 """ self.trace("jmpe r%d" % r1) if self.fl == 0: self.do_jmp_r1(r1, _) def do_jmpe_r2_r1(self, r1, r2): """jmpe r2:r1 """ self.trace("jmpe r%d:r%d" % (r2,r1)) if self.fl == 0: self.do_jmp_r2_r1(r1, r2) def do_hlt(self, _, __): """hlt N/A """ print "HALT!" self.dump_core("final") raise SystemExit(0) def decode(self): """ Read the next instruction from memory and decode it instruction encoding ++++++++++++++++++++ byte 1 byte 2 (optional) bits [ 7 6 5 4 3 2 1 0 ] [ 7 6 5 4 3 2 1 0 ] opcode - - - mod - operand1 - - - - operand2 - - - - - - - - operand1 is always a register index operand2 is optional, depending upon the instruction set specified below the value of mod alters the meaning of any operand2 0: operand2 = reg ix 1: operand2 = fixed immediate value or target segment (depending on instruction) instruction set +++++++++++++++ Notes: * r1, r2 => operand 1 is register 1, operand 2 is register 2 * movr r1, r2 => move contents of register r2 into register r1 opcode | instruction | operands (mod 0) | operands (mod 1) -------+-------------+------------------+----------------- 0x00 | jmp | r1 1 | r2:r1 2 0x01 | movr | r1, r2 2 | rx, imm 2 0x02 | movm | r1, [ds:r2] 2 | [ds:r1], r2 2 0x03 | add | r1, r2 2 | r1, imm 2 0x04 | xor | r1, r2 2 | r1, imm 2 0x05 | cmp | r1, r2 2 | r1, imm 2 0x06 | jmpe | r1 1 | r2:r1 2 0x07 | hlt | N/A 1 | N/A 1 """ self.instruction_ip = self.ip op1 = self.read_op() opcode = (op1 >> 5) & 0x7 mod = (op1 >> 4) & 0x1 operand1 = op1 & 0xF if opcode != HLT: assert operand1 < 6, "Out of range register" if opcode in (JMP, JMPE) and mod == 0: operand2 = None else: operand2 = self.read_op() self.dispatch[(opcode, mod)](operand1, operand2) def run(self): """Run the VM until halt""" try: while True: self.decode() self.cycle_count += 1 if (self.cycle_count & 0xFFFF) == 0: self.dump_core("%010X" % self.cycle_count) except Exception, e: self.debug = True self.trace("") self.dump_core("exception") raise def dump_core(self, name): """Dump the memory""" print "Dumping core %s" % name fd = open(name+".core", "wb") fd.write(self.mem) fd.close() if __name__ == "__main__": vm = VM(debug=True) vm.dump_core("initial") vm.run()